1 ps8319 05/03/00 pi6c184-02 precision 1-13 clock buffer pin configuration 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1 2345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012 12345678901 2 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 block diagram description ? high speed, low noise non-inverting 1-13 buffer ? supports up to four sdram dimms ? low skew (<250ps) between any two output clocks ? i 2 c serial configuration interface ? multiple v dd , v ss pins for noise reduction ? 3.3v power supply voltage ? 28-pin ssop and soic packages (h, s) the pi6c184-02 is a high-speed low-noise 1-13 non-inverting buffer designed for sdram clock buffer applications. this buffer is intended to be used with the pi6c104 clock generator for intel architecture for both desktop and mobile systems. at power up all sdram output are enabled and active. the i 2 c serial control may be used to individually activate/deactivate any of the 13 output drivers. note: purchase of i 2 c components from pericom conveys a license to use them in an i 2 c system as defined by philips. features sdram12 sdram2 sdram1 sdram0 buf_in sdata sclock sdram3 i 2 c i/o 1 2 3 v ss 4 v dd 5 sdram1 6 sdram3 7 v ss 8 sdram2 9 sdram4 10 sdram5 11 sdram12 12 v dd 13 sdata 14 v dd sdram10 v ss sdram9 sdram8 v ss v dd 28 sdram7 27 sdram6 26 v ss 25 v ss 24 sclk 23 22 21 20 19 18 17 16 15 v dd sdram0 buf_in v dd sdram11 28-pin h, s
2 ps8319 05/03/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c184-02 precision 1-13 clock buffer pin description p i6c184-02 i 2 c address assignment 6 a5 a4 a3 a2 a1 a0 aw / r 1101001 0 pi6c184 serial configuration map byte0: sdram active/inactive register (1 = enable, 0 = disable) note: inactive means outputs are held low and are disabled from switching n i pl o b m y se p y ty t i t n a u qn o i t p i r c s e d , 1 1 , 0 1 , 7 , 6 , 3 , 2] 5 . 0 [ m a r d s06 t u p t u o k c o l c 0 e t y b m a r d s 7 2 , 6 2 , 3 2 , 2 2 , 9 1 , 8 1] 1 1 . 6 [ m a r d s06 t u p t u o k c o l c 1 e t y b m a r d s 2 1] 2 1 [ m a r d s01 t u p t u o k c o l c 2 e t y b m a r d s 9n i _ f u b11 r e f f u b - 3 1 - 1 r o f t u p n i 4 1a t a d so / i1 i r o f n i p a t a d 2 k 0 0 1 a s a h . y r t i u c r i c c r o t s i s e r p u - l l u p l a n r e t n i 4 5 1k c o l c so / i1 i r o f n i p k c o l c 2 a s a h . y r t i u c r i c c r o t s i s e r p u - l l u p l a n r e t n i k 0 0 1 8 2 , 4 2 , 0 2 , 3 1 , 5 , 1v d d r e w o p6 r e f f u b m a r d s r o f y l p p u s r e w o p v 3 . 3 5 2 , 1 2 , 7 1 , 6 1 , 8 , 4v s s d n u o r g6 s r e f f u b m a r d s r o f d n u o r g t i b# n i pn o i t p i r c s e d 7 t i b1 1) e v i t c a n i / e v i t c a ( 5 m a r d s 6 t i b0 1) e v i t c a n i / e v i t c a ( 4 m a r d s 5 t i b~ d e v r e s e r 4 t i b~ d e v r e s e r 3 t i b7 ) e v i t c a n i / e v i t c a ( 3 m a r d s 2 t i b6 ) e v i t c a n i / e v i t c a ( 2 m a r d s 1 t i b3 ) e v i t c a n i / e v i t c a ( 1 m a r d s 0 t i b2 ) e v i t c a n i / e v i t c a ( 0 m a r d s
3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ps8319 05/03/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c184-02 precision 1-13 clock buffer byte1: sdram active/inactive register (1 = enable, 0 = disable) byte2: optional register for possible future requirements (1 = enable, 0 = disable) the i 2 c interface permits individual enable/disable of each clock output and test mode enable. the pi6c184-02 is a slave receiver device. it can not be read back. sub addressing is not supported. all preceding bytes must be sent in order to change one of the control bytes. every bite put on the sdata line must be 8-bits long (msb first), followed by an acknowledge bit generated by the receiving device. during normal data transfers sdata changes only when sclk is low. exceptions: a high to low transition on sdata while sclk is high indicates a start condition. a low to high transition on sdata while sclk is high is a stop condition and indicates the end of a data transfer cycle. each data transfer is initiated with a start condition and ended with a stop condition. the first byte after a start condition is always a 7-bit address byte followed by a read/write bit. (high = read from addressed device, low = write to addressed device). if the devices own address is detected, pi6c184-02 generates an acknowledge by pulling sdata line low during ninth clock pulse, then accepts the following data bytes until another start or stop condition is detected. following ack nowledgement of the address byte (d2), two more bytes must be sent: 1. command code byte, and 2. byte count byte. although the data bits on these two bytes are dont care, they must be sent and acknowledged. 2-wire i 2 c control maximum ratings (above which the useful life may be impaired. for user guidelines, not tested.) storage temperature ................................................ C65c to +150c ambient temperature with power applied ............. C0c to +70c 3.3v supply voltage to ground potential ............... C0.5v to +4.6v dc input voltage ..................................................... C0.5v to +4.6v note: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for ex- tended periods may affect reliability. supply current (v dd = +3.465v, cload = max) t i b# n i pn o i t p i r c s e d 7 t i b7 2) e v i t c a n i / e v i t c a ( 1 1 m a r d s 6 t i b6 2) e v i t c a n i / e v i t c a ( 0 1 m a r d s 5 t i b3 2) e v i t c a n i / e v i t c a ( 9 m a r d s 4 t i b2 2) e v i t c a n i / e v i t c a ( 8 m a r d s 3 t i ba / n) d e v r e s e r ( 2 t i ba / n) d e v r e s e r ( 1 t i b9 1) e v i t c a n i / e v i t c a ( 7 m a r d s 0 t i b8 1) e v i t c a n i / e v i t c a ( 6 m a r d s t i b# n i pn o i t p i r c s e d 7 t i ba / n) d e v r e s e r ( 6 t i b2 1) e v i t c a n i / e v i t c a ( 2 1 m a r d s 5 t i ba / n) d e v r e s e r ( 4 t i ba / n) d e v r e s e r ( 3 t i ba / n) d e v r e s e r ( 2 t i ba / n) d e v r e s e r ( 1 t i ba / n) d e v r e s e r ( 0 t i ba / n) d e v r e s e r ( l o b m y sr e t e m a r a pn o i t i d n o c t s e t. n i m. p y tx a ms t i n u i d d t n e r r u c y l p p u sz h m 0 = n i _ f u b3 a m i d d t n e r r u c y l p p u sz h m 6 6 . 6 6 = n i _ f u b0 3 2 i d d t n e r r u c y l p p u sz h m 0 . 0 0 1 = n i _ f u b0 6 3
4 ps8319 05/03/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c184-02 precision 1-13 clock buffer sdram clock buffer operating specification dc operating specifications (v dd = +3.3v 5%, t a = 0c - 70c) l o b m y sr e t e m a r a pn o i t i d n o c. n i m. p y t. x a ms t i n u i n i m h o t n e r r u c p u - l l u pv t u o v 0 . 2 =4 5 ? a m i x a m h o t n e r r u c p u - l l u pv t u o v 5 3 1 . 3 =6 4 ? i n i m l o t n e r r u c n w o d - l l u pv t u o v 0 . 1 =4 5 i x a m l o t n e r r u c n w o d - l l u pv t u o v 4 . 0 =3 5 t h r m a r d s e t a r e g d e e s i r t u p t u o y l n o m a r d s % 5 v 3 . 3 v 4 . 2 - v 4 0 @ 5 . 14 s n / v t h f m a r d s e t a r e g d e l l a f t u p t u o y l n o m a r d s % 5 v 3 . 3 v 4 . 0 - v 4 . 2 @ 5 . 14 l o b m y sr e t e m a r a pn o i t i d n o c t s e t. n i m. x a ms t i n u v , e g a t l o v t u p n i e r o c d d % 5 v 3 . 3 = ] 1 - 0 [ v h i e g a t l o v h g i h t u p n iv d d 0 . 2v e r o c d d 3 . 0 + v v l i e g a t l o v w o l t u p n iv s s 3 . 0 ?8 . 0 i l i t n e r r u c e g a k a e l t u p n iv < 0 n i v < d d 5 -5 + v d d % 5 v 3 . 3 = v h o e g a t l o v h g i h t u p t u oi h o a m 1 ? =4 . 2 v v l o e g a t l o v w o l t u p t u oi l o a m 1 ? =4 . 0 c n i e c n a t i c a p a c n i p t u p n i5 f p c t u o e c n a t i c a p a c s n i p t u p t u o6 l n i p e c n a t c u d n i n i p7h n t a e r u t a r e p m e t t n e i b m aw o l f r i a o n00 7c o l o b m y sr e t e m a r a p z h m 6 6z h m 0 0 1 s t i n u . n i m. x a m. n i m. x a m p k d s td o i r e p k l c m a r d s0 . 5 15 . 5 10 . 0 15 . 0 1 s n h k d s te m i t h g i h k l c m a r d s6 . 53 . 3 l k d s te m i t w o l k l c m a r d s3 . 51 . 3 e s i r d s te m i t e s i r k l c m a r d s5 . 10 . 45 . 10 . 4 s n / v l l a f d s te m i t l l a f k l c m a r d s5 . 10 . 45 . 10 . 4 h l p ty a l e d p o r p h l r e f f u b m a r d s0 . 10 . 50 . 10 . 5 s n l h p ty a l e d p o r p l h r e f f u b m a r d s0 . 10 . 50 . 10 . 5 h z p t , l z p ty a l e d e l b a n e r e f f u b m a r d s0 . 10 . 80 . 10 . 8 z h p t , z l p ty a l e d e l b a s i d r e f f u b m a r d s0 . 10 . 80 . 10 . 8 e l c y c y t u dv 5 . 1 t a d e r u s a e m5 45 55 45 5% w k s d s t o t t u p t u o m a r d s w e k s t u p t u o 0 5 20 5 2s p ac timing
5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ps8319 05/03/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c184-02 precision 1-13 clock buffer 1.5v 1.5v t phl t plh 1.5v 1.5v input waveform output waveform output buffer test point 2.4 1.5 0.4 tsdkh tsdkp 3.3v clocking interface (ttl) tsdkl t sdfall t sdrise test load figure 1. clock waveforms notes: 1. maximum rise/fall times are guaranteed at maximum specified load. 2. minimum rise/fall times are guaranteed at minimum specified load. 3. rise/fall times are specified with pure capacitive load as shown. testing is done with an additional 500 w resistor in parallel. minimum and maximum expected capacitive loads design guidelines to reduce emi 1. place series resistors and ci capacitors as close as possible to the respective clock pins. typical value for ci is 10 pf. series resistor value can be increased to reduce emi provided that the rise and fall time are still within the specified values. 2. minimize the number of vias of the clock traces. 3. route clock traces over a continuous ground plane or over a continuous power plane. avoid routing clock traces from plane to plane (refer to rule #2). 4. position clock signals away from signals that go to any cables or any external connectors. k c o l cd a o l n i md a o l x a ms t i n us e t o n m a r d s0 20 3f p m m i d m a r d s n o i t a c i f i c e p s
6 ps8319 05/03/00 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901 2123456789012 pi6c184-02 precision 1-13 clock buffer pericom semiconductor corporation 2380 bering drive ? san jose, ca 95131 ? 1-800-435-2336 ? fax (408) 435-1100 ? http://www.pericom.com ordering information figure 2. design guidelines sdram 22 w 13 ci pi6c184 sdram dimm spec. 100/66 mhz clock from chipset n / pn o i t p i r c s e d h 2 0 - 4 8 1 c 6 i pe g a k c a p p o s s n i p - 8 2 s 2 0 - 4 8 1 c 6 i pe g a k c a p c i o s n i p - 8 2 .390 .413 .078 .002 seating plane .0098 max. .0256 bsc .022 .037 .004 .009 .291 .322 1 28 .197 .220 0.25 x.xx x.xx denotes dimensions in millimeters 0.050 7.40 8.20 0.55 0.95 0.09 0.25 5.00 5.60 2.0 9.90 10.50 0.65 max min seating plane .050 bsc 1 0-8? .2914 .2992 x.xx x.xx denotes dimensions in millimeters 7.40 7.60 .6969 .7125 17.70 18.10 1.27 .0926 .1043 2.35 2.65 .394 .419 10.00 10.65 .0040 .0118 0.10 0.30 .013 .020 0.33 0.51 .010 .029 0.254 0.737 .0091 .0125 0.23 0.32 0.41 1.27 .016 .050 x 45? 28 .021 .031 0.533 0.787 ref 28-pin ssop (h) 28-pin soic (s)
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